High-quality digital telecommunications and recording systems require channels capable of reliably supporting high-data rates. For example, transmission rates for high definition television (HDTV) signals may range from 150 megabits-per-second (Mb/s) to more than 1000 Mb/s, while some digital video applications require high-density, magnetic recording at rates in excess of 200 Mb/s.
With high-density recording, closely-situated flux transitions overlap and produce interference, i.e., intersymbol interference, between the symbols they represent. Intersymbol interference may arise because of insufficient bandwidth at head-medium channels (for recording applications) and transmission channels (for telecommunication applications).
Performance of high-data rate channels may be increased through use of Class-4 partial response (PR4) coding in a data storage or transmission channel using a data detector configured to implement a Viterbi algorithm during data retrieval or reception. Specifically, PR4 coding controls intersymbol interference at limited bandwidth while allowing a significant increase in the data rates of the channels. Moreover, partial-response coding provides high correlation between data sequences, thereby facilitating prediction of erroneous data values.
A PR4 waveform is a 3-valued (ternary) signal having "high", "middle" or "low" values, where a "high" or "low" value is a binary "1" and a "middle" value is a "0". The PR4 waveform is derived from a binary waveform by subtracting, from the binary waveform, a 2-bit interval, delayed version of itself. Before re-conversion to binary format, the PR4 data stream is decomposed into successions derived from alternate samples. These "even" and "odd" successions of samples conform to the sequence property of PR4 coding which states that "high" and "low" signals must alternate and may be separated by any number of "middle" values.
The Viterbi algorithm provides an iterative method of determining the maximum-likelihood sequences of these alternate data samples, despite interference, and Viterbi detectors/decoders operate to process the data sequences in accordance with the algorithm. An example of a conventional Viterbi decoder is set forth in an article titled, The Viterbi detection of class 4 partial response on the magnetic recording channel, by Roger Wood and David Peterson, IEEE Transactions on Communications, vol. COMM-34, no. 5 (1986).
The Wood et al. Viterbi decoder comprises an A/D conversion circuit, Viterbi logic and a random-access memory (RAM). The Viterbi logic block includes a single processing path of logic devices coupled to the RAM. Circuit operation is basically asynchronous since re-clocking occurs only after signal processing. Moreover, the circuit includes a feedback loop for calculating various threshold levels needed for Viterbi decoding; this feedback loop contributes significant delays to the operation of the decoder. Accordingly, these factors impact reliable sequence detection operations at high frequencies and the present invention is directed to improving the speed and reliability of maximum likelihood sequence detection and correction.